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authortzlil <tzlils@protonmail.com>2024-03-22 15:29:21 +0200
committertzlil <tzlils@protonmail.com>2024-03-22 15:29:21 +0200
commitfde8f4b6420689a5e4e45700b8618cb014a7bf06 (patch)
treea1f740da92f302e242bc602b240a3b8ea0bd642a /src/Blinker.hs
parentb42198bf82068f3e5cc1751a3641a36b4234f14c (diff)
remove I2C crap and get to work
Diffstat (limited to 'src/Blinker.hs')
-rw-r--r--src/Blinker.hs62
1 files changed, 22 insertions, 40 deletions
diff --git a/src/Blinker.hs b/src/Blinker.hs
index 6242f30..4537fb7 100644
--- a/src/Blinker.hs
+++ b/src/Blinker.hs
@@ -10,7 +10,6 @@ import Clash.Prelude
 import Clash.Annotations.SynthesisAttributes
 import Clash.Cores.UART
 import Control.Monad.Trans.State.Strict
-import I2C (i2cMaster, Message)
 
 
 -- 50 MHz
@@ -21,85 +20,68 @@ createDomain vSystem{vName="Input", vPeriod=20_000}
     { t_name   = "Blinker"
     , t_inputs = [
       PortName "CLK0",
-      PortName "UART_RX"
+      PortName "UART_RX",
+      PortName "KEY0",
+      PortName "I2C_SCL",
+      PortName "I2C_SDA"
        ]
     , t_output = PortName "UART_TX"
     }) #-}
 topEntity ::
-  "CLK" ::: Clock Input
+  "CLK0" ::: Clock Input
     `Annotate` 'StringAttr "chip_pin" "R20"
     `Annotate` 'StringAttr
                 "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\""
-  -> "RX" ::: Signal Input Bit
-    `Annotate` 'StringAttr
-                "chip_pin" "M9"
+  -> "UART_RX" ::: Signal Input Bit
+    `Annotate` 'StringAttr "chip_pin" "M9"
     `Annotate` 'StringAttr
                 "altera_attribute" "-name IO_STANDARD \"2.5V\""
   -> "KEY0" ::: Signal Input Bit
-    `Annotate` 'StringAttr
-                "chip_pin" "P11"
+    `Annotate` 'StringAttr "chip_pin" "P11"
     `Annotate` 'StringAttr
                 "altera_attribute" "-name IO_STANDARD \"1.2V\""
   -> "I2C_SCL" ::: BiSignalIn 'PullUp Input (BitSize Bit)
-    `Annotate` 'StringAttr
-                "chip_pin B7"
+    `Annotate` 'StringAttr "chip_pin" "B7"
     `Annotate` 'StringAttr
                 "altera_attribute" "-name IO_STANDARD \"2.5V\""
   -> "I2C_SDA" ::: BiSignalIn 'PullUp Input (BitSize Bit)
-    `Annotate` 'StringAttr
-                "chip_pin G11"
+    `Annotate` 'StringAttr "chip_pin" "G11"
     `Annotate` 'StringAttr
                 "altera_attribute" "-name IO_STANDARD \"2.5V\""
-  -> (Signal Input Bit
-    `Annotate` 'StringAttr
-                "chip_pin" "L9"
-    `Annotate` 'StringAttr
-                "altera_attribute" "-name IO_STANDARD \"2.5V\""
-    ,"I2C_SCL" ::: BiSignalOut 'PullUp Input (BitSize Bit)
-    `Annotate` 'StringAttr
-                "chip_pin B7"
-    `Annotate` 'StringAttr
-                "altera_attribute" "-name IO_STANDARD \"2.5V\""
-    ,"I2C_SDA" ::: BiSignalOut 'PullUp Input (BitSize Bit)
-    `Annotate` 'StringAttr
-                "chip_pin G11"
+  ->
+    "UART_TX" ::: Signal Input Bit
+    `Annotate` 'StringAttr "chip_pin" "L9"
     `Annotate` 'StringAttr
                 "altera_attribute" "-name IO_STANDARD \"2.5V\""
-    )
-topEntity clk rx key0 sclIn sdaIn = (txBit,sclOut,sdaOut)
+topEntity clk rx key0 sclIn sdaIn = (txBit)
   where
     baud = SNat @115200
     uart' = exposeClockResetEnable (uart baud) clk resetGen enableGen
     (rxWord, txBit, ackUART) = uart' rx txM
-    (sclOut, sdaOut, ackI2C) = exposeClockResetEnable (i2cMaster (SNat @20_000) i2cM sclIn sdaIn) clk resetGen enableGen
-    f = exposeClockResetEnable mealyS clk resetGen enableGen cpu Initialization (CPUIn <$> key0 <*> ackUART <*> ackI2C <*> rxWord)
-    (txM,i2cM) = unbundle f
+    f = exposeClockResetEnable mealyS clk resetGen enableGen cpu Initialization (CPUIn <$> key0 <*> ackUART <*> rxWord)
+    txM = unbundle f
 
 
 data CPUIn = CPUIn {
   key0 :: Bit,
   ackUART :: Bool,
-  ackI2C :: Bool,
   rx :: Maybe (BitVector 8)
 }
 
-type CPUOut = (Maybe (BitVector 8),Maybe Message)
+type CPUOut = Maybe (BitVector 8)
 
 data CPUState = Initialization
                 | TransmittingUART (BitVector 8)
-                | TransmittingI2C Message
                 | Listening 
                 deriving (Generic, NFDataX)
 cpu :: CPUIn -> State CPUState CPUOut
 cpu CPUIn{rx=Just rx} = do
   put $ TransmittingUART rx
-  return (Nothing, Nothing)
+  return Nothing
 
-cpu CPUIn{ackUART=True} = put Listening >> return (Nothing, Nothing)
-cpu CPUIn{ackI2C=True} = put Listening >> return (Nothing, Nothing)
+cpu CPUIn{ackUART=True} = put Listening >> return Nothing
 
 cpu _ = get >>= \case
-  Initialization -> put Listening >> return (Nothing, Nothing)
-  TransmittingUART s -> return (Just s, Nothing)
-  TransmittingI2C s -> return (Nothing, Just s)
-  Listening -> return (Nothing, Nothing)
+  Initialization -> put Listening >> return Nothing
+  TransmittingUART s -> return $ Just s
+  Listening -> return Nothing