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| author | tzlil <tzlils@protonmail.com> | 2024-02-23 16:28:14 +0200 |
|---|---|---|
| committer | tzlil <tzlils@protonmail.com> | 2024-02-23 16:28:14 +0200 |
| commit | 2d3e55c69d8ff08af0bc0363dd70879b8b6dc873 (patch) | |
| tree | b28fec165e5681a5b239e24c12d61872f79ccb77 | |
| parent | d06c0fa5a036ea068487b260e004dc5da8f92fb9 (diff) | |
rename stuff, add SSAM2603 ADC/DAC chip docs
| -rw-r--r-- | fpga.cabal (renamed from blinker.cabal) | 2 | ||||
| -rw-r--r-- | src/Main.hs (renamed from src/Blinker.hs) | 4 | ||||
| -rw-r--r-- | ssm2603.pdf | bin | 0 -> 509001 bytes |
3 files changed, 3 insertions, 3 deletions
diff --git a/blinker.cabal b/fpga.cabal index 35e0781..14ac474 100644 --- a/blinker.cabal +++ b/fpga.cabal @@ -83,5 +83,5 @@ common common-options library import: common-options hs-source-dirs: src - exposed-modules: Blinker + exposed-modules: Main default-language: Haskell2010 \ No newline at end of file diff --git a/src/Blinker.hs b/src/Main.hs index 9dc9778..43f4746 100644 --- a/src/Blinker.hs +++ b/src/Main.hs @@ -4,7 +4,7 @@ {-# LANGUAGE FlexibleContexts #-} {-# LANGUAGE LambdaCase #-} {-# OPTIONS_GHC -option #-} -module Blinker where +module Main where import Clash.Prelude import Clash.Annotations.SynthesisAttributes @@ -17,7 +17,7 @@ createDomain vSystem{vName="Input", vPeriod=20_000} {-# ANN topEntity (Synthesize - { t_name = "Blinker" + { t_name = "Main" , t_inputs = [ PortName "CLK0", PortName "UART_RX" diff --git a/ssm2603.pdf b/ssm2603.pdf new file mode 100644 index 0000000..5699e03 --- /dev/null +++ b/ssm2603.pdf Binary files differ |