diff options
| author | tzlil <tzlils@protonmail.com> | 2024-02-23 16:28:14 +0200 |
|---|---|---|
| committer | tzlil <tzlils@protonmail.com> | 2024-02-23 16:28:14 +0200 |
| commit | 2d3e55c69d8ff08af0bc0363dd70879b8b6dc873 (patch) | |
| tree | b28fec165e5681a5b239e24c12d61872f79ccb77 /src | |
| parent | d06c0fa5a036ea068487b260e004dc5da8f92fb9 (diff) | |
rename stuff, add SSAM2603 ADC/DAC chip docs
Diffstat (limited to 'src')
| -rw-r--r-- | src/Main.hs (renamed from src/Blinker.hs) | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Blinker.hs b/src/Main.hs index 9dc9778..43f4746 100644 --- a/src/Blinker.hs +++ b/src/Main.hs @@ -4,7 +4,7 @@ {-# LANGUAGE FlexibleContexts #-} {-# LANGUAGE LambdaCase #-} {-# OPTIONS_GHC -option #-} -module Blinker where +module Main where import Clash.Prelude import Clash.Annotations.SynthesisAttributes @@ -17,7 +17,7 @@ createDomain vSystem{vName="Input", vPeriod=20_000} {-# ANN topEntity (Synthesize - { t_name = "Blinker" + { t_name = "Main" , t_inputs = [ PortName "CLK0", PortName "UART_RX" |