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author | tzlil <tzlils@protonmail.com> | 2024-02-26 19:32:41 +0200 |
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committer | tzlil <tzlils@protonmail.com> | 2024-02-26 19:32:41 +0200 |
commit | b42198bf82068f3e5cc1751a3641a36b4234f14c (patch) | |
tree | f751e58112a7c0e377fa8024a79e6bc1cc6b6d98 | |
parent | c596dd198c36cd4c9e82cfbc93d0dd003fdc4b4c (diff) |
fix i2c lol I2C
-rw-r--r-- | src/Blinker.hs | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/Blinker.hs b/src/Blinker.hs index 365012a..6242f30 100644 --- a/src/Blinker.hs +++ b/src/Blinker.hs @@ -55,12 +55,12 @@ topEntity :: "chip_pin" "L9" `Annotate` 'StringAttr "altera_attribute" "-name IO_STANDARD \"2.5V\"" - ,"I2C_SCL" ::: BiSignalIn 'PullUp Input (BitSize Bit) + ,"I2C_SCL" ::: BiSignalOut 'PullUp Input (BitSize Bit) `Annotate` 'StringAttr "chip_pin B7" `Annotate` 'StringAttr "altera_attribute" "-name IO_STANDARD \"2.5V\"" - ,"I2C_SDA" ::: BiSignalIn 'PullUp Input (BitSize Bit) + ,"I2C_SDA" ::: BiSignalOut 'PullUp Input (BitSize Bit) `Annotate` 'StringAttr "chip_pin G11" `Annotate` 'StringAttr @@ -72,7 +72,8 @@ topEntity clk rx key0 sclIn sdaIn = (txBit,sclOut,sdaOut) uart' = exposeClockResetEnable (uart baud) clk resetGen enableGen (rxWord, txBit, ackUART) = uart' rx txM (sclOut, sdaOut, ackI2C) = exposeClockResetEnable (i2cMaster (SNat @20_000) i2cM sclIn sdaIn) clk resetGen enableGen - (txM,i2cM) = exposeClockResetEnable mealyS clk resetGen enableGen cpu Initialization (CPUIn <$> key0 <*> (ackUART,ackI2C) <*> rxWord) + f = exposeClockResetEnable mealyS clk resetGen enableGen cpu Initialization (CPUIn <$> key0 <*> ackUART <*> ackI2C <*> rxWord) + (txM,i2cM) = unbundle f data CPUIn = CPUIn { @@ -91,7 +92,7 @@ data CPUState = Initialization deriving (Generic, NFDataX) cpu :: CPUIn -> State CPUState CPUOut cpu CPUIn{rx=Just rx} = do - put $ Transmitting rx + put $ TransmittingUART rx return (Nothing, Nothing) cpu CPUIn{ackUART=True} = put Listening >> return (Nothing, Nothing) |