{-# LANGUAGE ImplicitParams #-}
{-# LANGUAGE NumericUnderscores #-}
{-# LANGUAGE AllowAmbiguousTypes #-}
{-# LANGUAGE FlexibleContexts #-}
{-# LANGUAGE LambdaCase #-}
{-# OPTIONS_GHC -option #-}
module Blinker where

import Clash.Prelude
import Clash.Annotations.SynthesisAttributes
import Clash.Cores.UART
import Control.Monad.Trans.State.Strict


-- 50 MHz
createDomain vSystem{vName="Input", vPeriod=20_000}

{-# ANN topEntity
  (Synthesize
    { t_name   = "Blinker"
    , t_inputs = [
      PortName "CLK0",
      PortName "UART_RX",
      PortName "KEY0",
      PortName "I2C_SCL",
      PortName "I2C_SDA"
       ]
    , t_output = PortName "UART_TX"
    }) #-}
topEntity ::
  "CLK0" ::: Clock Input
    `Annotate` 'StringAttr "chip_pin" "R20"
    `Annotate` 'StringAttr
                "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\""
  -> "UART_RX" ::: Signal Input Bit
    `Annotate` 'StringAttr "chip_pin" "M9"
    `Annotate` 'StringAttr
                "altera_attribute" "-name IO_STANDARD \"2.5V\""
  -> "KEY0" ::: Signal Input Bit
    `Annotate` 'StringAttr "chip_pin" "P11"
    `Annotate` 'StringAttr
                "altera_attribute" "-name IO_STANDARD \"1.2V\""
  -> "I2C_SCL" ::: BiSignalIn 'PullUp Input (BitSize Bit)
    `Annotate` 'StringAttr "chip_pin" "B7"
    `Annotate` 'StringAttr
                "altera_attribute" "-name IO_STANDARD \"2.5V\""
  -> "I2C_SDA" ::: BiSignalIn 'PullUp Input (BitSize Bit)
    `Annotate` 'StringAttr "chip_pin" "G11"
    `Annotate` 'StringAttr
                "altera_attribute" "-name IO_STANDARD \"2.5V\""
  ->
    "UART_TX" ::: Signal Input Bit
    `Annotate` 'StringAttr "chip_pin" "L9"
    `Annotate` 'StringAttr
                "altera_attribute" "-name IO_STANDARD \"2.5V\""
topEntity clk rx key0 sclIn sdaIn = (txBit)
  where
    baud = SNat @115200
    uart' = exposeClockResetEnable (uart baud) clk resetGen enableGen
    (rxWord, txBit, ackUART) = uart' rx txM
    f = exposeClockResetEnable mealyS clk resetGen enableGen cpu Initialization (CPUIn <$> key0 <*> ackUART <*> rxWord)
    txM = unbundle f


data CPUIn = CPUIn {
  key0 :: Bit,
  ackUART :: Bool,
  rx :: Maybe (BitVector 8)
}

type CPUOut = Maybe (BitVector 8)

data CPUState = Initialization
                | TransmittingUART (BitVector 8)
                | Listening 
                deriving (Generic, NFDataX)
cpu :: CPUIn -> State CPUState CPUOut
cpu CPUIn{rx=Just rx} = do
  put $ TransmittingUART rx
  return Nothing

cpu CPUIn{ackUART=True} = put Listening >> return Nothing

cpu _ = get >>= \case
  Initialization -> put Listening >> return Nothing
  TransmittingUART s -> return $ Just s
  Listening -> return Nothing