From 7be1c699f018d96540d76e67ad7254bafe4caab1 Mon Sep 17 00:00:00 2001 From: tzlil Date: Thu, 16 Nov 2023 19:29:37 +0200 Subject: inital commit --- src/Blinker.hs | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/Blinker.hs (limited to 'src') diff --git a/src/Blinker.hs b/src/Blinker.hs new file mode 100644 index 0000000..30e6f0e --- /dev/null +++ b/src/Blinker.hs @@ -0,0 +1,32 @@ +{-# OPTIONS_GHC -fno-warn-orphans #-} +module Blinker where + +import Clash.Prelude +import Clash.Annotations.SynthesisAttributes + +-- Define a synthesis domain with a clock with a period of 20000 /ps/. +-- i.e. 50 MHz +-- createDomain vSystem{vName="Input", vPeriod=20000} + +-- Define a synthesis domain with a clock with a period of 50000 /ps/. +-- i.e. 20 MHz +createDomain vSystem{vName="Dom20MHz", vPeriod=50000} + +{-# ANN topEntity + (Synthesize + { t_name = "Blinker" + , t_inputs = [ PortName "KEY0" ] + , t_output = PortName "LED" + }) #-} +topEntity :: + Signal Dom20MHz Bit + `Annotate` 'StringAttr "chip_pin" "AC9" + `Annotate` 'StringAttr + "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" -> + + Signal Dom20MHz Bit + `Annotate` 'StringAttr + "chip_pin" "F7" + `Annotate` 'StringAttr + "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" +topEntity sw = sw \ No newline at end of file -- cgit 1.4.1