From 5c6635052b6983d2149b936762298200f6419275 Mon Sep 17 00:00:00 2001 From: tzlil Date: Fri, 26 Jan 2024 21:09:09 +0200 Subject: UART ECHO SERVER!!!!!!!! --- .gitignore | 2 +- C5G_User_Manual.pdf | Bin 0 -> 11013365 bytes ...ll for FPGA Hardware Design-Leanpub (2021).pdf" | Bin 0 -> 6533904 bytes blinker.cabal | 3 + flake.lock | 31 +++++++++-- flake.nix | 7 ++- notes.txt | 17 ++++++ src/Blinker.hs | 62 +++++++++++++-------- 8 files changed, 92 insertions(+), 30 deletions(-) create mode 100644 C5G_User_Manual.pdf create mode 100644 "Gerg\305\221 \303\211rdi - Retrocomputing with Clash_ Haskell for FPGA Hardware Design-Leanpub (2021).pdf" create mode 100644 notes.txt diff --git a/.gitignore b/.gitignore index 16023c9..b3b7e72 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,3 @@ result .direnv -dist-newstyle \ No newline at end of file +dist-newstyle diff --git a/C5G_User_Manual.pdf b/C5G_User_Manual.pdf new file mode 100644 index 0000000..4836e86 Binary files /dev/null and b/C5G_User_Manual.pdf differ diff --git "a/Gerg\305\221 \303\211rdi - Retrocomputing with Clash_ Haskell for FPGA Hardware Design-Leanpub (2021).pdf" "b/Gerg\305\221 \303\211rdi - Retrocomputing with Clash_ Haskell for FPGA Hardware Design-Leanpub (2021).pdf" new file mode 100644 index 0000000..a4c51af Binary files /dev/null and "b/Gerg\305\221 \303\211rdi - Retrocomputing with Clash_ Haskell for FPGA Hardware Design-Leanpub (2021).pdf" differ diff --git a/blinker.cabal b/blinker.cabal index 3a2d389..35e0781 100644 --- a/blinker.cabal +++ b/blinker.cabal @@ -70,9 +70,12 @@ common common-options build-depends: base, Cabal, + mtl, + transformers, -- clash-prelude will set suitable version bounds for the plugins clash-prelude >= 1.8.1 && < 1.10, + clash-cores, ghc-typelits-natnormalise, ghc-typelits-extra, ghc-typelits-knownnat diff --git a/flake.lock b/flake.lock index f6b8125..e5a1ece 100644 --- a/flake.lock +++ b/flake.lock @@ -1,15 +1,33 @@ { "nodes": { + "clash-cores": { + "flake": false, + "locked": { + "dir": "clash-cores", + "lastModified": 1705612353, + "narHash": "sha256-rdoIaLLOlZKTL7mFj6KVfo8WfRNB2Z0kldMCLI1OMDI=", + "owner": "clash-lang", + "repo": "clash-compiler", + "rev": "5e01ae2aec13f7b91cc8a6f5475feb4f24bf50b5", + "type": "github" + }, + "original": { + "dir": "clash-cores", + "owner": "clash-lang", + "repo": "clash-compiler", + "type": "github" + } + }, "flake-utils": { "inputs": { "systems": "systems" }, "locked": { - "lastModified": 1694529238, - "narHash": "sha256-zsNZZGTGnMOf9YpHKJqMSsa0dXbfmxeoJ7xHlrt+xmY=", + "lastModified": 1705309234, + "narHash": "sha256-uNRRNRKmJyCRC/8y1RqBkqWBLM034y4qN7EprSdmgyA=", "owner": "numtide", "repo": "flake-utils", - "rev": "ff7b65b44d01cf9ba6a71320833626af21126384", + "rev": "1ef2e671c3b0c19053962c07dbda38332dcebf26", "type": "github" }, "original": { @@ -20,11 +38,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1699781429, - "narHash": "sha256-UYefjidASiLORAjIvVsUHG6WBtRhM67kTjEY4XfZOFs=", + "lastModified": 1705496572, + "narHash": "sha256-rPIe9G5EBLXdBdn9ilGc0nq082lzQd0xGGe092R/5QE=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "e44462d6021bfe23dfb24b775cc7c390844f773d", + "rev": "842d9d80cfd4560648c785f8a4e6f3b096790e19", "type": "github" }, "original": { @@ -36,6 +54,7 @@ }, "root": { "inputs": { + "clash-cores": "clash-cores", "flake-utils": "flake-utils", "nixpkgs": "nixpkgs" } diff --git a/flake.nix b/flake.nix index 1517d5a..b07c283 100644 --- a/flake.nix +++ b/flake.nix @@ -2,9 +2,13 @@ inputs = { nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable"; flake-utils.url = "github:numtide/flake-utils"; + clash-cores = { + url = "github:clash-lang/clash-compiler?dir=clash-cores"; + flake = false; + }; }; - outputs = { nixpkgs, flake-utils, self }: + outputs = { clash-cores, nixpkgs, flake-utils, self }: flake-utils.lib.eachDefaultSystem (system: let name = "Blinker"; @@ -31,6 +35,7 @@ ver = "1.8.1"; sha256 = "sha256-/dFgCj9e+gkyyUDAB1n1ukaEnkugCR7cRkP+SFJmjjY="; } {}; + clash-cores = super.callCabal2nix "clash-cores" "${clash-cores}/clash-cores/" { }; }; }; hpkg = pkgs.haskell.lib.overrideCabal (hpkgs.callCabal2nix name src {}) (drv: { diff --git a/notes.txt b/notes.txt new file mode 100644 index 0000000..ca7f978 --- /dev/null +++ b/notes.txt @@ -0,0 +1,17 @@ +get the quartus toolchain from nixpkgs +NIXPKGS_ALLOW_UNFREE=1 nix shell --impure nixpkgs#quartus-prime-lite + +get clash +nix shell github:clash-lang/clash-compiler + +blink example clash +https://qbaylogic.com/all/clash/new-clash-fpga-starter/ + +write a .sof file to the fpga over jtag +quartus_pgm -m jtag -o "p;blinker.sof" + +compile a whole project +quartus_sh --flow compile blinker + +the one i have is: +Cyclone V 5CGXFC5C6F27C7 diff --git a/src/Blinker.hs b/src/Blinker.hs index 8980763..7ee5ff8 100644 --- a/src/Blinker.hs +++ b/src/Blinker.hs @@ -1,47 +1,65 @@ -{-# OPTIONS_GHC -fno-warn-orphans #-} {-# LANGUAGE ImplicitParams #-} -{-# LANGUAGE FlexibleContexts #-} {-# LANGUAGE NumericUnderscores #-} {-# LANGUAGE AllowAmbiguousTypes #-} +{-# LANGUAGE FlexibleContexts #-} +{-# OPTIONS_GHC -option #-} module Blinker where import Clash.Prelude import Clash.Annotations.SynthesisAttributes +import Clash.Cores.UART +import Data.Char (ord) +import Control.Monad.Trans.State.Strict -createDomain vSystem{vName="Input", vPeriod=20000} - --- createDomain vSystem{vName="Dom20MHz", vPeriod=50000} +-- 50 MHz +createDomain vSystem{vName="Input", vPeriod=20_000} {-# ANN topEntity (Synthesize { t_name = "Blinker" , t_inputs = [ PortName "CLK0", - PortName "KEY0" + PortName "UART_RX" ] - , t_output = PortName "LED" + , t_output = PortName "UART_TX" }) #-} topEntity :: - HiddenClockResetEnable Input => - Clock Input + "CLK" ::: Clock Input `Annotate` 'StringAttr "chip_pin" "R20" `Annotate` 'StringAttr - "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" -> - Signal Input Bit - `Annotate` 'StringAttr "chip_pin" "AC9" + "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" + -> "RX" ::: Signal Input Bit `Annotate` 'StringAttr - "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" -> - - Signal Input Bit + "chip_pin" "M9" `Annotate` 'StringAttr - "chip_pin" "F7" + "altera_attribute" "-name IO_STANDARD \"2.5V\"" + -> "KEY0" ::: Signal Input Bit `Annotate` 'StringAttr - "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" -topEntity clk sw = msb <$> r + "chip_pin" "P11" + `Annotate` 'StringAttr + "altera_attribute" "-name IO_STANDARD \"1.2V\"" + -> Signal Input Bit + `Annotate` 'StringAttr + "chip_pin" "L9" + `Annotate` 'StringAttr + "altera_attribute" "-name IO_STANDARD \"2.5V\"" +topEntity clk rx key0 = txBit where - r :: Signal Input (Unsigned 24) - r = withClockResetEnable clk resetGen enableGen $ register 0 (r + 1) + baud = SNat @115200 + uart' = exposeClockResetEnable (uart baud) clk resetGen enableGen + (rxWord, txBit, ack) = uart' rx txM + txM = (exposeClockResetEnable mealySB clk resetGen enableGen) (uncurry cpu) Nothing (ack,rxWord) + +type CpuState = Maybe (BitVector 8) +cpu :: Bool -> Maybe (BitVector 8) -> State CpuState (Maybe (BitVector 8)) +cpu _ (Just rx) = do + put (Just rx) + return Nothing +cpu True Nothing = do + put Nothing + return Nothing --- graph :: Signal Dom20MHz (Unsigned 8) -> Signal Dom20MHz (Maybe ((Unsigned 8), Term)) -> Signal Dom20MHz Term --- graph = asyncRam d32 \ No newline at end of file +cpu False Nothing = do + s <- get + return s \ No newline at end of file -- cgit 1.4.1