From 3b5936958c72d7f4db1b5d0deb00cdb43a2f5e66 Mon Sep 17 00:00:00 2001
From: tzlil <tzlils@protonmail.com>
Date: Fri, 17 Nov 2023 05:10:05 +0200
Subject: Das Blinknlights!

---
 src/Blinker.hs | 35 +++++++++++++++++++++++++----------
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/src/Blinker.hs b/src/Blinker.hs
index 30e6f0e..8980763 100644
--- a/src/Blinker.hs
+++ b/src/Blinker.hs
@@ -1,32 +1,47 @@
 {-# OPTIONS_GHC -fno-warn-orphans #-}
+{-# LANGUAGE ImplicitParams #-}
+{-# LANGUAGE FlexibleContexts #-}
+{-# LANGUAGE NumericUnderscores #-}
+{-# LANGUAGE AllowAmbiguousTypes #-}
 module Blinker where
 
 import Clash.Prelude
 import Clash.Annotations.SynthesisAttributes
 
--- Define a synthesis domain with a clock with a period of 20000 /ps/.
--- i.e. 50 MHz
--- createDomain vSystem{vName="Input", vPeriod=20000}
+createDomain vSystem{vName="Input", vPeriod=20000}
 
--- Define a synthesis domain with a clock with a period of 50000 /ps/.
--- i.e. 20 MHz
-createDomain vSystem{vName="Dom20MHz", vPeriod=50000}
+-- createDomain vSystem{vName="Dom20MHz", vPeriod=50000}
 
 {-# ANN topEntity
   (Synthesize
     { t_name   = "Blinker"
-    , t_inputs = [ PortName "KEY0" ]
+    , t_inputs = [
+      PortName "CLK0",
+      PortName "KEY0"
+       ]
     , t_output = PortName "LED"
     }) #-}
 topEntity ::
-  Signal Dom20MHz Bit
+  HiddenClockResetEnable Input =>
+  Clock Input
+    `Annotate` 'StringAttr "chip_pin" "R20"
+    `Annotate` 'StringAttr
+                "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" ->
+  Signal Input Bit
     `Annotate` 'StringAttr "chip_pin" "AC9"
     `Annotate` 'StringAttr
                 "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" ->
 
-  Signal Dom20MHz Bit
+  Signal Input Bit
     `Annotate` 'StringAttr
                 "chip_pin" "F7"
     `Annotate` 'StringAttr
                 "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\""
-topEntity sw = sw
\ No newline at end of file
+topEntity clk sw = msb <$> r
+  where
+    r :: Signal Input (Unsigned 24)
+    r = withClockResetEnable clk resetGen enableGen $ register 0 (r + 1)
+
+
+-- graph :: Signal Dom20MHz (Unsigned 8) -> Signal Dom20MHz (Maybe ((Unsigned 8), Term)) -> Signal Dom20MHz Term
+-- graph = asyncRam d32
\ No newline at end of file
-- 
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